1. Field of the Invention
The invention relates to frequency synthesizers and methods of synthesizing frequencies in a wireless communication system, and more particularly to a dual frequency synthesizer included in a transceiver having a single shared sigma-delta modulator and methods of synthesizing a frequency using the same.
2. Description of the Related Art
In wireless communication systems, frequency synthesizers for obtaining (channel) frequencies necessary for a transmitter and a receiver are necessary. Each frequency synthesizer uses a phase-locked loop (PLL) to generate a desired channel frequency by way of comparing a signal of a reference frequency with a divided frequency signal (which is an oscillation frequency of a voltage controlled oscillator (VCO) that is divided at a necessary frequency divide ratio).
Phase-locked loops used in frequency synthesis methods can be an integer-N type or a fractional-N type.
The integer-N type method, in which the oscillation frequency of the voltage controlled oscillator is divided by an integer division ratio, has a drawback in that the resolution of the phase-locked loop is constrained to be an integer-N times the reference frequency. In the integer-N type phase-locked loop, the reference frequency must be small so as to achieve a desired fine frequency resolution. This obstructs the use of a high loop bandwidth. There is a degradation of locking time of the phase-locked because the loop bandwidth and locking time of the phase-locked loop have an inversely proportional relationship to each other.
On the other hand, the fractional-N type method is capable of dividing the oscillation frequency of the voltage controlled oscillator by a divide ratio having a fractional value. Accordingly, it can be advantageous in the locking time of the phase-locked loop because a high reference frequency can be used and thus the high loop bandwidth can be chosen. Also, by increasing the reference frequency, the fractional-N type has an advantage with respect to in-band noise. This is particularly true, in a wireless communication system having a relatively narrow channel bandwidth such as a wireless communication system using a code division multiple access (CDMA) technology. Thus, the fractional-N type method in which the reference frequency is not limited by the channel bandwidth is essential to such a wireless communication system.
In addition, the fractional-N type PLL employs the method of continuously switching the divide ratio to predetermined integer values to obtain a desired average divide ratio so that a desired non-integer (fractional) divide ratio may be achieved. A sigma-delta modulator configured to perform noise-shaping is used to remove spurious noise, by continuously switching the divide ratio with a pseudo-random modulation.
FIG. 1 is a block diagram illustrating a conventional fractional-N phase-locked loop.
Referring to FIG. 1, the fractional-N phase-locked loop includes a phase detector PD 101, a loop filter 102 and a voltage controlled oscillator VCO 103 that are similar in form and function to analogous elements of a general (integer-N) phase-locked loop. The fractional-N phase-locked loop further includes an N′ counter 104, an N′ decoder 105 and a sigma-delta modulator 106.
The division ratio of the fractional-N phase-locked loop is represented by the sum of an integer division ratio N and a fractional division ratio Fract that is between zero and one. The integer division ratio N is inputted to the N′ decoder 105 and the fractional division ratio Fract is inputted to the sigma-delta modulator 106. The sigma-delta modulator 106 may include a multilevel adder and a latch that operate in synchronization with an output clock of the N′ counter 104 to output an add signal or a subtract signal to the N′ decoder 105.                The N′ decoder 105 decodes the add signal or the subtract signal outputted from the sigma-delta modulator 106 to add or subtract a predetermined value from the integer division ratio N, and generates an integer division ratio N′. The N′ counter 104 receives the integer division ratio N′, which varies in predetermined sequences, from the N′ decoder 105, and based on the integer division ratio N′, the N′ decoder 105 divides an output clock of the voltage controlled oscillator VCO 103. Thus, on average, the fractional-N phase-locked loop performs a fractional-N division operation.        
Although the fractional-N phase-locked loop has some advantages as mentioned above, the fractional-N phase-locked loop has the disadvantage of a larger chip size because the sigma-delta modulator included in the fractional-N phase-locked loop has a relatively large area on the chip.
FIG. 2 is a block diagram illustrating a conventional dual frequency synthesizer 200 using two conventional fractional-N phase-locked loops and two sigma-delta demodulators.
Referring to FIG. 2, the conventional dual frequency synthesizer 200 includes a first phase-locked loop Rx PLL 210 and a first sigma delta modulator 218 (for a receiving channel) and a second phase-locked loop Tx PLL 250 and a second sigma delta modulator 258 (for a transmitting channel).
The phase-locked loop Rx PLL 210 for the receiving channel includes a temperature compensation crystal oscillator TCXO 211, an R counter 212, a phase detector and charge pump PFD/CP 213, a loop filter LPF 214, a voltage controlled oscillator 215, an N′ counter 216, an N′ decoder 217 and a sigma-delta modulator 218.
Similarly, the phase-locked loop Tx PLL 250 for the transmitting channel includes a temperature compensation crystal oscillator TCXO 251, an R counter 252, a phase detector and charge pump PFD/CP 253, a loop filter LPF 254, a voltage controlled oscillator 255, an N′ counter 256, an N′ decoder 257 and a sigma-delta modulator 258.
Although it is illustrated that the PLLs (Rx PLL and Tx PLL) for the receiving and transmitting channels have separate temperature compensation crystal oscillators TCXO in FIG. 2, the temperature compensation crystal oscillator TCXO may be shared by the two PLLs in common in an typical application.
As shown in FIG. 2, two sigma-delta modulators 218 and 258 are used for the fractional-N frequency synthesizer because each PLL for the receiving and transmitting channels operates independently, resulting in an increase in chip size. Each sigma-delta modulator takes up about one third of the chip size of the frequency synthesizer so that the fractional-N frequency synthesizer has a increased chip size compared with the integer-N frequency synthesizer.